1. Field of the Invention
The present invention relates to a ring-based architecture for providing access to internal registers and/or memories located on an integrated circuit chip.
2. Related Art
Most reasonably complex chip designs require software access to internal registers/memories for initialization, configuration, status retrieval and debugging purposes. Such register/memory access been provided in many different ways in the past.
FIG. 1 is a block diagram of a conventional chip 100, which includes register/memory access logic 101, functional blocks 111-113, management port 121, SM bus master 131 and SM bus slave 132. Functional blocks 111-113 include registers and/or memory, which can be accessed directly via a functional path, or indirectly through register/memory access logic 101. Indirect access is facilitated by interface modules, such as management port 121, SM bus master 131 and SM bus slave 132, which are coupled to register/memory access logic 101.
Direct access is achieved by an off-chip controller 140, which can be, for example, a root complex coupled to functional block 113 via a functional path, such as a PCIe port or an AS port.
Indirect access can be achieved by another off-chip controller 150 (e.g., on-board processor) coupled to management port 121 via a management path, such as a PCIe port. Indirect access can also be achieved by yet another off-chip controller 152 (e.g., SM bus master) coupled to SMbus slave 132 via a SM bus. Indirect access can also be achieved through SM bus master 151, which is coupled to an external EEPROM 151 (e.g., SM bus slave) via a SM bus.
Register/memory access logic 101 can be implemented in many different manners. For example, all registers/memories on chip 100 may be centrally located, and access to these registers/memories can be performed by a single controller within register/memory access logic 101. While this scheme is conceptually simple, large physical design constraints are placed on the overall chip design. For example, the inputs of all the registers/memories need to be routed through the chip from where they are sourced. Likewise, the outputs of all the registers/memories need to be routed through the chip to where they are used. Thus, an excessive number of wires may be required, thereby making the timing of this scheme difficult to implement.
Registers/memories can also be distributed in many separate modules that are all connected by a single parallel bus. Logic attempting to access the distributed registers/memories must arbitrate with other logic to gain access to the parallel bus. This scheme places the registers/memories close to where they are used, and thus reduces both wiring and timing issues. However, the parallel bus must be relatively large, both in terms of bus width and distance traversed by the bus on the chip. With such a configuration, a large number of slaves and masters coupled to the parallel bus will create loading and timing problems. Moreover, only one transaction can occur at any given time with the scheme. In addition, a central arbiter may be required for the various masters to arbitrate for the parallel bus.
It would therefore be desirable to have an access system having a generic and flexible architecture and design, such that the access system can be reused in multiple chip designs. It would further be desirable for the access system to provide a mechanism for accessing all of the accessible on-chip registers and memory locations in a uniform manner. It would also be desirable if the access system is transparent to the chip designer whose application modules require access to the on-chip registers and memory locations, such that the designer only needs to input a list of register/memory locations and the associated addresses prior to connecting the module to the access system. It would also be desirable for the access system to be optimized in terms of area and routing, and also operate with a reasonable latency.